1. Field of the Invention
This invention relates to a data processing apparatus with an input/output (I/O) device and a data processing method.
2. Description of the Related Art
An I/O device, e.g., disk controller, network controller, etc. is usually connected to a bus. Since the number of devices connectable to a bus is restricted by an electrical condition of the bus, number of control signals, etc., the number of the devices connected to the bus is limited.
The number of devices connectable to the bus can be increased by layering the bus. The layered bus is called as a hierarchical bus, hereinafter. In the hierarchical bus, a bus coupler is provided between a bus at an upper layer and a bus at a lower layer. The bus coupler relays data from a bus to an appropriate bus based on a destination address of the data transmitted in the bus.
FIG. 23 illustrates a data transfer system with the hierarchical bus according to the related art. In FIG. 23, disk controllers and magnetic disk drives (or also called as disk drives, hereinafter) controlled by the disk controllers are provided as the I/O devices for example. Normally, an origin or destination of a data transfer is a main memory, and the main memory is shared by all the I/O devices. Therefore, the main memory is connected to a top layer in the hierarchical bus.
Operations are explained with reference to FIG. 23.
Data in files 61a-61f in disk drives 8a-8f are transferred to buffers 10a-10f in a main memory 2, and processed by a central processing unit (CPU) 1.
The CPU 1 requests a disk controller 7a to transfer the data in the file 61a in the disk drive 8a to the buffer 10a. The disk controller 7a transfers the data to an I/O bus 5a. An I/O bus coupler 6a relays the data from the I/O bus 5a to an I/O bus 5d. A system bus-I/O bus coupler 4 relays the data from the I/O bus 5d to a system bus 3. Then, the data are stored in the buffer 10a in the main memory 2.
The CPU 1 also requests a disk controller 7b to transfer the data in the file 61b in the disk drive 8b to the buffer 10b. The disk controller 7b transfers the data to the I/O bus 5a. The I/O bus coupler 6a relays the data from the I/O bus 5a to the I/O bus 5d. The system bus-I/O bus coupler 4 relays the data from the I/O bus 5d to the system bus 3. Then, the data are stored in the buffer 10b in the main memory 2.
The CPU 1 also requests a disk controller 7c to transfer the data in the file 61c in the disk drive 8c to the buffer 10c. The disk controller 7c transfers the data to an I/O bus 5b. An I/O bus coupler 6b relays the data from the I/O bus 5b to the I/O bus 5d. The system bus-I/O bus coupler 4 relays the data from the I/O bus 5d to the system bus 3. Then, the data are stored in the buffer 10c in the main memory 2.
The CPU 1 also requests a disk controller 7d to transfer the data in the file 61d in the disk drive 8d to the buffer 10d. The disk controller 7d transfers the data to the I/O bus 5b. The I/O bus coupler 6b relays the data from the I/O bus 5b to the I/O bus 5d. The system bus-I/O bus coupler 4 relays the data from the I/O bus 5d to the system bus 3. Then, the data are stored in the buffer 10d in the main memory 2.
The CPU 1 also requests a disk controller 7e to transfer the data in the file 61e in the disk drive 8e to the buffer 10e. The disk controller 7e transfers the data to an I/O bus 5c. An I/O bus coupler 6c relays the data from the I/O bus 5c to the I/O bus 5d. The system bus-I/O bus coupler 4 relays the data from the I/O bus 5d to the system bus 3. Then, the data are stored in the buffer 10e in the main memory 2.
The CPU 1 also requests a disk controller 7f to transfer the data in the file 61f in the disk drive 8f to the buffer 10f. The disk controller 7f transfers the data to the I/O bus 5c. The I/C bus coupler 6c relays the data from the I/O bus 5c to the I/O bus 5d. The system bus-I/O bus coupler 4 relays the data from the I/C bus 5d to the system bus 3. Then, the data are stored in the buffer 10f in the main memory 2.
The CPU 1 processes the data transferred to the buffers 10a-10f, and stores a result from processing in a last output buffer 101.
As stated, the data are always transferred to the main memory 2 via the I/O bus 5d, system bus-I/O bus coupler 4, and system bus 3. The data transferred from all the I/O devices connected at lower layers in the hierarchical bus are channeled through the buses at upper layers in the hierarchical bus.
However, since data transfer in a bus per unit time is generally limited, data exceeding the limit cannot be transferred.
When a bus is occupied for a transfer of data, even if a transfer of other data is requested, the latter data cannot be transferred until the first data transfer is completed. When the data in the files 61a-61e are transferred at once, transfer speed of the data is restricted by transfer speeds of data in the I/O bus 5d and system bus 3. Therefore, even if the number of connectable devices is increased by adopting the hierarchical bus, the data transfer speed of the system is restricted by the transfer speed of the bus at the top layer. Hence, a data transfer speed appropriate for the number of devices cannot be realized.
In the hierarchical bus according to the related art, the CPU 1 processes all the data. Since the data processed by the CPU per unit time period is limited, data exceeding the limit cannot be processed. When the CPU 1 processes the data transferred from the files 61a-61e, a processing speed of the data is restricted by the processing speed of the CPU 1. Even if the number of connectable devices is increased by adopting the hierarchical bus, the processing speed of the system is restricted by the processing speed of the CPU, and the data processing speed appropriate for the number of devices cannot be realized.
The hierarchical bus according to the related art is configured as above stated, and all the transferred data are channeled through the buses at upper layers. Therefore, even if the number of connectable devices is increased, an appropriate data transfer speed cannot be realized.
The hierarchical bus according to the related art is configured as above stated, and the processing speed of data is restricted by the processing speed of the CPU. Therefore, even if the number of connectable devices is increased, an appropriate processing speed cannot be realized.